# ESP32-S3 CAN FD Logger - Pin Validation

## Hardware Configuration Overview

**Board**: ESP32-S3-WROOM-1-N16R8
- Flash: 16MB Quad SPI
- PSRAM: 8MB Octal SPI (uses GPIO33-37)
- Cores: Dual Xtensa LX7 @ 240MHz

## Pin Assignment Analysis

### HSPI (CAN FD MCP2518FD)
| Pin | GPIO | Function | Status | Notes |
|-----|------|----------|--------|-------|
| MISO | GPIO13 | SPI Data In | ✅ OK | - |
| MOSI | GPIO11 | SPI Data Out | ✅ OK | - |
| SCLK | GPIO12 | SPI Clock | ✅ OK | - |
| CS | GPIO10 | Chip Select | ✅ OK | - |
| INT | GPIO3 | Interrupt | ⚠️ OK | No USB conflict (USB not used) |

### SDIO 4-bit (SD Card)
| Pin | GPIO | Function | Status | Notes |
|-----|------|----------|--------|-------|
| CLK | GPIO39 | SDIO Clock | ✅ OK | - |
| CMD | GPIO38 | SDIO Command | ✅ OK | - |
| D0 | GPIO40 | SDIO Data 0 | ✅ OK | - |
| D1 | GPIO41 | SDIO Data 1 | ✅ OK | - |
| D2 | GPIO42 | SDIO Data 2 | ✅ OK | - |
| D3 | GPIO21 | SDIO Data 3 | ⚠️ WARNING | Strapping pin (see below) |

### I2C (DS3231 RTC)
| Pin | GPIO | Function | Status | Notes |
|-----|------|----------|--------|-------|
| SDA | GPIO8 | I2C Data | ✅ OK | - |
| SCL | GPIO9 | I2C Clock | ✅ OK | - |

## Critical Pin Analysis

### 1. PSRAM Conflict Check ✅
**PSRAM uses**: GPIO33, 34, 35, 36, 37

**Our pins**: GPIO3, 8, 9, 10, 11, 12, 13, 21, 38, 39, 40, 41, 42

**Result**: NO CONFLICT
- All our pins are outside the PSRAM range (33-37)
- SDIO pins (38-42, 21) are safe to use

### 2. GPIO21 (Strapping Pin) ⚠️
GPIO21 is a **strapping pin** used during boot:
- Internal pull-up resistor (~10kΩ)
- Used for boot mode selection
- Safe to use after boot initialization

**Recommendation**: 
- SDIO_D3 (GPIO21) will work correctly
- Pull-down resistor is already present in strapping logic
- No additional hardware changes needed

### 3. GPIO3 (INT Pin) ⚠️
GPIO3 is USB D- in USB mode:
- User confirmed: **USB NOT USED**
- USB CDC is used via Native USB (GPIO19/20)
- Safe to use GPIO3 for CAN interrupt

## Arduino IDE Configuration

### Board Settings
```
Board: ESP32S3 Dev Module
USB CDC On Boot: Enabled
CPU Frequency: 240MHz
Flash Mode: QIO 80MHz
Flash Size: 16MB (128Mb)
Partition Scheme: 16M Flash (3MB APP/9.9MB FAT)
PSRAM: OPI PSRAM
Upload Mode: UART0 / Hardware CDC
Upload Speed: 921600
```

### Why These Settings?
- **USB CDC On Boot**: Required for Serial.println() to work over USB
- **Partition Scheme 16M**: Maximizes available flash for app and SPIFFS
- **PSRAM OPI**: Required for 8MB Octal PSRAM operation
- **Upload Mode UART0**: Standard serial upload via USB

## Pin Mapping Reference

```
GPIO  Function        Status
----  --------        ------
3     CAN_INT         OK (USB unused)
8     RTC_SDA         OK
9     RTC_SCL         OK
10    HSPI_CS         OK
11    HSPI_MOSI       OK
12    HSPI_SCLK       OK
13    HSPI_MISO       OK
21    SDIO_D3         OK (Strapping pin)
38    SDIO_CMD        OK
39    SDIO_CLK        OK
40    SDIO_D0         OK
41    SDIO_D1         OK
42    SDIO_D2         OK

PSRAM Pins (DO NOT USE):
33-37 Reserved for Octal PSRAM
```

## Summary

✅ **All pins validated successfully**
- No PSRAM conflicts
- SDIO 4-bit mode pins are available
- CAN FD interrupt pin is safe (USB not used)
- RTC I2C pins are standard and available

⚠️ **Warnings (non-critical)**
- GPIO21 is strapping pin but safe for SDIO after boot
- GPIO3 would conflict with USB if USB Serial was used

**Hardware is ready for implementation.**